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R1LP0108E Series
1Mb Advanced LPSRAM (128k word x 8bit)
R10DS0029EJ0200 Rev.2.00 2011.01.14
Description
The R1LP0108E Series is a family of low voltage 1-Mbit static RAMs organized as 131,072-word by 8-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies. The R1LP0108E Series has realized higher density, higher performance and low power consumption. The R1LP0108E Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. It has been packaged in 32-pin SOP,32-pin TSOP and 32-pin sTSOP.
Features
* * * * * * * * Single 4.5~5.5V power supply Small stand-by current: 1A (5.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS1# and CS2 Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus
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R1LP0108E Series
Ordering Information
Orderable Part Name R1LP0108ESP-5SR#B0 55 ns R1LP0108ESP-5SI#B0 R1LP0108ESP-7SR#B0 70 ns R1LP0108ESP-7SI#B0 R1LP0108ESP-5SR#S0 55 ns R1LP0108ESP-5SI#S0 R1LP0108ESP-7SR#S0 70 ns R1LP0108ESP-7SI#S0 R1LP0108ESA-5SR#B0 55 ns R1LP0108ESA-5SI#B0 R1LP0108ESA-7SR#B0 70 ns R1LP0108ESA-7SI#B0 R1LP0108ESA-5SR#S0 55 ns R1LP0108ESA-5SI#S0 R1LP0108ESA-7SR#S0 70 ns R1LP0108ESA-7SI#S0 R1LP0108ESF-5SR#B0 55 ns R1LP0108ESF-5SI#B0 R1LP0108ESF-7SR#B0 70 ns R1LP0108ESF-7SI#B0 R1LP0108ESF-5SR#S0 55 ns R1LP0108ESF-5SI#S0 R1LP0108ESF-7SR#S0 70 ns R1LP0108ESF-7SI#S0 R1LP0108ESR-5SR#B0 55 ns R1LP0108ESR-5SI#B0 R1LP0108ESR-7SR#B0 70 ns R1LP0108ESR-7SI#B0 R1LP0108ESR-5SR#S0 55 ns R1LP0108ESR-5SI#S0 R1LP0108ESR-7SR#S0 70 ns R1LP0108ESR-7SI#S0 -40 ~ +85C -40 ~ +85C 0 ~ +70C -40 ~ +85C 0 ~ +70C PTSA0032KA-B (32P3H-F) Embossed tape 1000pcs/Reel -40 ~ +85C 0 ~ +70C 8mmx20mm 32-pin plastic TSOP (reverse-bend type) Tray Max. 156pcs/Tray Max. 1248pcs/Inner Box -40 ~ +85C 0 ~ +70C -40 ~ +85C 0 ~ +70C -40 ~ +85C 0 ~ +70C PTSA0032KA-A (32P3H-E) Embossed tape 1000pcs/Reel -40 ~ +85C 0 ~ +70C 8mmx20mm 32-pin plastic TSOP (normal-bend type) Tray Max. 156pcs/Tray Max. 1248pcs/Inner Box -40 ~ +85C 0 ~ +70C -40 ~ +85C 0 ~ +70C -40 ~ +85C 0 ~ +70C PTSA0032KB-A (32P3K-B) Embossed tape 1000pcs/Reel -40 ~ +85C 0 ~ +70C 8mmx13.4mm 32-pin plastic sTSOP (normal-bend type) Tray Max. 234pcs/Tray Max. 1872pcs/Inner Box -40 ~ +85C 0 ~ +70C -40 ~ +85C 0 ~ +70C -40 ~ +85C 0 ~ +70C -40 ~ +85C Tube 0 ~ +70C 525-mil 32-pin plastic SOP PRSP0032DA-A (32P2M-A) Access time Temperature Range 0 ~ +70C Max. 25pcs/Tube Max. 225pcs/Inner Bag Max. 900pcs/Inner Box Package Shipping Container Quantity
Embossed tape
1000pcs/Reel
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R1LP0108E Series
Pin Arrangement
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
Vcc A15 CS2 WE# A13 A8 A9 A11 OE# A10 CS1# DQ7 DQ6 DQ5 DQ4 DQ3
32-pin SOP
25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 WE# CS2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
OE# A10 CS1# DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
32-pin sTSOP
25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 WE# CS2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
OE# A10 CS1# DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
A4 A5 A6 A7 A12 A14 A16 NC Vcc A15 CS2 WE# A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
17 18 19 20 21 22 23
A3 A2 A1 A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 DQ7 CS1# A10 OE#
32-pin TSOP (normal-bend)
25 24 23 22 21 20 19 18 17
32-pin TSOP (reverse-bend)
24 25 26 27 28 29 30 31 32
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R1LP0108E Series
Pin Description
Pin name Vcc Vss A0 to A16 DQ0 to DQ7 CS1# CS2 WE# OE# NC Function Power supply Ground Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Non connection
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R1LP0108E Series
Block Diagram
A0 A1
ADDRESS BUFFER ROW DECODER MEMORY ARRAY 128k-word x8-bit
A16 DQ0
DQ BUFFER SENSE / WRITE AMPLIFIER
DQ1
DQ7
COLUMN DECODER
CLOCK GENERATOR
WE# CS1# CS2 OE#
Vcc Vss
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R1LP0108E Series
Operation Table
CS1# X H L L L Note 1. CS2 L X H H H H: VIH L:VIL WE# X X L H H OE# X X X L H DQ0~7 High-Z High-Z Din Dout High-Z Operation Stand-by Stand-by Write Read Output disable
X: VIH or VIL
Absolute Maximum
Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note Symbol Vcc VT PT Topr*3 Tstg Tbias*3 R Ver. I Ver. Value -0.3 to +7 -0.3*1 to Vcc+0.3*2 0.7 R Ver. 0 to +70 I Ver. -65 to 150 0 to +70 -40 to +85 -40 to +85 unit V V W C C C
1. -3.0V for pulse 30ns (full width at half maximum) 2. Maximum voltage is +7V. 3. Ambient temperature range depends on R/I-version. Please see table on page 1.
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R1LP0108E Series
DC Operating Conditions
Parameter Supply voltage Input high voltage Input low voltage Ambient temperature range Note R Ver. I Ver. Symbol Vcc Vss VIH VIL Ta Min. 4.5 0 2.2 -0.3 0 -40 Typ. 5.0 0 Max. 5.5 0 Vcc+0.3 0.8 +70 +85 Unit V V V V C C 1 2 2 Note
1. -3.0V for pulse 30ns (full width at half maximum) 2. Ambient temperature range depends on R/I-version. Please see table on page 1.
DC Characteristics
Parameter Input leakage current Output leakage current Symbol | ILI | | ILO | Average operating current Min. Typ. Max. 1 1 Unit A A Test conditions Vin = Vss to Vcc CS1# =VIH or CS2 =VIL or OE# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA CS1# =VIL, CS2 =VIH, Others = VIH/VIL Cycle =1s, duty =100%, II/O = 0mA CS1# 0.2V, CS2 Vcc-0.2V, VIH Vcc-0.2V, VIL 0.2V "CS2 =VIL" or "CS2 = VIH and CS1# =VIH", Others = Vss to Vcc ~+25C ~+40C ~+70C ~+85C IOH = -1mA IOH = -0.1mA IOL = 2mA Vin = Vss to Vcc
ICC1
-
25
35
mA
ICC2 Standby current ISB Standby current
-
2
5
mA
-
-
3
mA
ISB1 -
1*1 -
2 3 8 10 0.4
A A A A V V V
(1) CS2 0.2 or (2) CS1# Vcc-0.2V, CS2 Vcc-0.2V
Output high voltage
VOH VOH2
2.4 Vcc - 0.5 -
Output low voltage Note
VOL
1. Typical parameter indicates the value for the center of distribution at 5.0V (Ta= 25C), and not 100% tested.
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R1LP0108E Series
Capacitance
(Vcc = 4.5V ~ 5V, f = 1MHz, Ta = 0 ~ +70C / -40 ~ +85C*2)
Parameter Symbol Min. Typ. Max. Unit Test conditions Input capacitance C in 8 pF Vin =0V Input / output capacitance C I/O 10 pF VI/O =0V Note 1. This parameter is sampled and not 100% tested. 2. Ambient temperature range depends on R/I-version. Please see table on page 1. Note 1 1
AC Characteristics
Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = 0 ~ +70C / -40 ~ +85C*1) * * * * Input pulse levels: VIL = 0.6V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V
RL = 500 ohm DQ CL = 30 pF CL = 100 pF
Note
( -5SI, -5SR) ( -7SI, -7SR)
1. Ambient temperature range depends on R/I-version. Please see table on page 1.
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R1LP0108E Series Read Cycle
Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol tRC tAA tACS1 tACS2 tOE tOH tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ
R1LP0108E**-5S* R1LP0108E**-7S*
Min. 55 5 5 5 5 0 0 0
Max. 55 55 55 30 20 20 20
Min. 70 10 10 10 5 0 0 0
Max. 70 70 70 35 25 25 25
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Note
2,3 2,3 2,3 1,2,3 1,2,3 1,2,3
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R1LP0108E Series Write Cycle
Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Note Symbol tWC tAW tCW tWP tAS tWR tDW tDH tOW tOHZ tWHZ
R1LP0108E**-5S* R1LP0108E**-7S*
Min. 55 50 50 45 0 0 25 0 5 0 0
Max. 20 20
Min. 70 55 55 50 0 0 30 0 5 0 0
Max. 25 25
Unit ns ns ns ns ns ns ns ns ns ns ns
Note
5 4 6 7
2 1,2 1,2
1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#. A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low. A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. 8. Don't apply inverted phase signal externally when DQ pin is output mode.
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R1LP0108E Series
Timing Waveforms
Read Cycle
tRC
A0~16 tAA tOH
CS1# tCLZ1
tACS1 tCHZ1
CS2 tCLZ2 WE#
WE# = "H" level VIH
tACS2 tCHZ2
OE# tOLZ High impedance DQ0~7
tOE tOHZ
Valid Data
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R1LP0108E Series Write Cycle (1) (WE# CLOCK)
tWC
A0~16 tCW CS1# tCW
CS2 tAW tAS WE# tWP tWR
OE# tWHZ tOHZ DQ0~7 tOW tOLZ
Valid Data tDW tDH
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R1LP0108E Series Write Cycle (2) (CS1#, CS2 CLOCK)
tWC A0~16 tAW tAS CS1# tAS CS2 tWP WE# tCW tWR tCW tWR
OE#
OE# = "H" level
VIH
tDW DQ0~7
tDH
Valid Data
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R1LP0108E Series
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions*2 Vin 0V (1) 0V CS2 0.2V or (2) CS1# Vcc-0.2V, CS2 Vcc-0.2V ~+25C Vcc=3.0V, Vin 0V Data retention current ICCDR Chip deselect to data retention time Operation recovery time Note tCDR tR 0 5 8 10 A A ns ms ~+70C ~+85C See retention waveform. 3 A ~+40C (1) 0V CS2 0.2V or (2) CS1# Vcc-0.2V, CS2 Vcc-0.2V
VCC for data retention
VDR
2.0
-
5.5
V
-
1*1
2
A
1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25C), and not 100% tested. 2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 Vcc-0.2V or 0V CS2 0.2V. The other input levels (address, WE# ,OE#, DQ) can be in the high impedance state.
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R1LP0108E Series Low Vcc Data Retention Timing Waveforms (1) CS1# Controlled Vcc
tCDR
2.2V
4.5V
4.5V
tR
2.2V
VDR
CS1# Vcc - 0.2V
CS1#
(2) CS2 Controlled Vcc CS2
tCDR
4.5V
4.5V
tR
VDR
0.2V 0.2V
0V CS2 0.2V
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Revision History
R1LP0108E Series Data Sheet
Description Summary First Edition issued Ordering Information is revised
Rev. 1.00 2.00
Date 2010.10.20 2011.01.14
Page 2
All trademarks and registered trademarks are the property of their respective owners.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 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